Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization
| Autor: | Tugba Demirci, Yusuf Leblebici, Thomas LaGrange, Elmira Shahrabi |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Materials science
tungsten reram mechanism integration Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 01 natural sciences Barrier layer Reliability (semiconductor) 0103 physical sciences cmos Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering 010302 applied physics model business.industry post-processing 021001 nanoscience & nanotechnology Condensed Matter Physics Chip Atomic and Molecular Physics and Optics Line (electrical engineering) Surfaces Coatings and Films Electronic Optical and Magnetic Materials Resistive random-access memory CMOS resistive switching memory Electrode Optoelectronics interface engineering Performance improvement 0210 nano-technology business devices |
| Zdroj: | Microelectronic Engineering. 214:74-80 |
| ISSN: | 0167-9317 |
| DOI: | 10.1016/j.mee.2019.04.018 |
| Popis: | The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, time and cost effective integration technique and at the same time provide device stability with CMOS-compatible materials that are used in the relevant device applications. In this study, we demonstrate a technique for the nm-scale hybrid integration of ReRAM on the foundry-produced CMOS 180 nm technology chip. Tungsten (W), as a material of choice for vertical vias in CMOS circuitry, is employed as the ReRAM electrode. However, W oxidizes readily, having multiple oxidation states, which influences the device reliability. In particular, the generation of semi-stable oxides at the electrode/switching layer (W/HfO2) interface has a profound influence on device performance. To achieve reliable W-based integrated ReRAM, we modulated and controlled the W electrode oxidation within the different co-integrated ReRAM stacks by increasing HfO2 switching layer thickness, through the post-metallization annealing under O2-ambient, and by adding an Al2O3 barrier layer between the W and HfO2 layers. The effect of W interface modifications is further studied through the analysis of switching mechanism and TEM micro-structural characterization. A notable improvement in HRS/LRS resistance ratio and switching stability was observed in optimally fabricated (W/Al2O3/HfO2/TiN) ReRAM on the back end of the line (BEoL) of 180 nm CMOS chip. |
| Databáze: | OpenAIRE |
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