Compact Modeling of Perpendicular-Magnetic-Anisotropy Double-Barrier Magnetic Tunnel Junction With Enhanced Thermal Stability Recording Structure

Autor: Zhizhong Zhang, Dafiné Ravelosona, Jacques-Olivier Klein, Yue Zhang, Zhenyi Zheng, Weisheng Zhao, Kun Zhang, Guanda Wang, Jinkai Wang, Youguang Zhang
Přispěvatelé: Department of Math and Computer Science, Center of Network, Henan Police College, EAST CHINA UNIVERSITY, KEY LAB, Centre de Nanosciences et de Nanotechnologies [Orsay] (C2N), Université Paris-Sud - Paris 11 (UP11)-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS), Institut d'électronique fondamentale (IEF), Université Paris-Sud - Paris 11 (UP11)-Centre National de la Recherche Scientifique (CNRS), Fert Beijing Institute and School of Electronic and Information Engineering, Beihang University (BUAA)
Rok vydání: 2019
Předmět:
Zdroj: IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2019, 66 (5), pp.2431-2436. ⟨10.1109/TED.2019.2906932⟩
ISSN: 1557-9646
0018-9383
DOI: 10.1109/ted.2019.2906932
Popis: As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs.
Databáze: OpenAIRE