Modeling and Simulation of Digital Phase-Locked Loop in Simulink
| Autor: | D. Nielinaer, Volker Christ, Markus Robens, Nina Parkalian, S. van Waasen, C. Grewinz, Pavithra Muralidharan, A. Zambanini, Daniel Liebau, U. Yegin |
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| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Bandwidth (signal processing) Process (computing) 02 engineering and technology Noise shaping Modeling and simulation Phase-locked loop Phase noise 0202 electrical engineering electronic engineering information engineering Electronic engineering Oversampling Block (data storage) Elektrotechnik |
| Zdroj: | SMACD |
| Popis: | This paper presents a high-level model for a digital phase-locked loop implemented in Simulink. This modeling enables the flexible and fast estimation of the design behavior and parameters before transistor-level implementation. The design includes a digital controlled oscillator that is defined using a linear s-domain model. Furthermore, the design of a time-to-digital converter based on oversampling and noise shaping is introduced to increase the effective resolution of the block. The simulation results of locking process, stability and phase noise verify the functionality of the model. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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