Some Algorithms for Computing Short-Length Linear Convolution
| Autor: | Janusz P. Paplinski, Aleksandr Cariow |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Very-large-scale integration
Adder convolution neural networks Computer Networks and Communications Computer science 020208 electrical & electronic engineering lcsh:Electronics lcsh:TK7800-8360 020206 networking & telecommunications 02 engineering and technology Short length Chip linear convolution algorithms Power (physics) Set (abstract data type) Hardware and Architecture Control and Systems Engineering Signal Processing 0202 electrical engineering electronic engineering information engineering Multiplier (economics) fast hardware-oriented computations Electrical and Electronic Engineering Algorithm |
| Zdroj: | Electronics Volume 9 Issue 12 Electronics, Vol 9, Iss 2115, p 2115 (2020) |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics9122115 |
| Popis: | In this article, we propose a set of efficient algorithmic solutions for computing short linear convolutions focused on hardware implementation in VLSI. We consider convolutions for sequences of length N= 2, 3, 4, 5, 6, 7, and 8. Hardwired units that implement these algorithms can be used as building blocks when designing VLSI -based accelerators for more complex data processing systems. The proposed algorithms are focused on fully parallel hardware implementation, but compared to the naive approach to fully parallel hardware implementation, they require from 25% to about 60% less, depending on the length N and hardware multipliers. Since the multiplier takes up a much larger area on the chip than the adder and consumes more power, the proposed algorithms are resource-efficient and energy-efficient in terms of their hardware implementation. |
| Databáze: | OpenAIRE |
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