A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
| Autor: | Osman Unsal, Oscar Palomar, Cristóbal Ramírez, César Alejandro Hernández, Adrian Cristal, Marco A. Leyva Ramírez |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| Rok vydání: | 2020 |
| Předmět: |
FOS: Computer and information sciences
Computer science Vector architectures 02 engineering and technology gem5 01 natural sciences Set (abstract data type) High performance computing -- Research Hardware Architecture (cs.AR) Vectorization 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Architecture Computer Science - Hardware Architecture Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Simulation High-performance computer architecture 010302 applied physics Suite Benchmarking Base (topology) 020202 computer hardware & architecture Hardware and Architecture RISC-V Vectorization (mathematics) Benchmark (computing) Superordinadors -- Investigació Software Information Systems |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| ISSN: | 1544-3973 1544-3566 |
| Popis: | Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that includes a flexible and customizable vector architecture model. In consequence, researchers have to develop their own simulation platform to test their ideas, which consume much research time. However, once the base simulator platform is developed, another question is the following: Which applications should be tested to perform the experiments? The lack of Vectorized Benchmark Suites is another limitation. To face these problems, this work presents a set of tools for designing and evaluating vector architectures. First, the gem5 simulator was extended to support the execution of RISC-V Vector instructions by adding a parameterizable Vector Architecture model for designers to evaluate different approaches according to the target they pursue. Second, a novel Vectorized Benchmark Suite is presented: a collection composed of seven data-parallel applications from different domains that can be classified according to the modules that are stressed in the vector architecture. Finally, a study of the Vectorized Benchmark Suite executing on the gem5-based Vector Architecture model is highlighted. This suite is the first in its category that covers the different possible usage scenarios that may occur within different vector architecture designs such as embedded systems, mainly focused on short vectors, or High-Performance-Computing (HPC), usually designed for large vectors. Comment: ACM Transactions on Architecture and Code Optimization, Volume 17, Issue 4, December 2020, Article No.38 |
| Databáze: | OpenAIRE |
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