Low-Power Divider Retiming in a 3-4GHz Fractional-N PLL
| Autor: | A.L. Lacaita, Marco Zanuso, Carlo Samori, Salvatore Levantino, Davide Tasca |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2011 |
| Předmět: |
Frequency synthesizer
Engineering sezele metastability frequency synthesizer synchronization PLL business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Noise (electronics) Phase-locked loop Frequency divider Low-power electronics Phase noise Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering Retiming business Jitter |
| Popis: | The resynchronization of a frequency divider output is routinely used in the design of low-noise phase-locked loops (PLLs) in order to remove additional phase noise and avoid modulus-dependent nonlinearity. However, metastability issues cause PLLs to fail to lock or to degrade jitter at certain synthesized frequencies. This brief proposes a novel automatic retiming circuit, which mitigates metastability issues and avoids induced noise degradation, without adding a relevant increase in power consumption. A 3-4-GHz PLL implementing this technique has been fabricated in 65-nm CMOS technology. Measured root mean square jitter below 500 fsec over the whole tuning range and added current consumption of 51 μA from a voltage supply of 1.2 V prove the effectiveness of the proposed solution. |
| Databáze: | OpenAIRE |
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