A RISC architecture extended by an efficient tightly coupled reconfigurable unit

Autor:	Nikolaos Vassiliadis, George Theodoridis, Spyridon Nikolaidis, Nikolaos Kavvadias
Rok vydání:	2006
Předmět:	Speedup Reduced instruction set computing business.industry Computer science Pipeline (computing) Embedded system Datapath Control unit Overhead (computing) Electrical and Electronic Engineering business Instruction-level parallelism Reconfigurable computing
Zdroj:	Scopus-Elsevier
ISSN:	1362-3060 0020-7217
DOI:	10.1080/00207210600565127
Popis:	In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain reconfigurable functional unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminate the communication overhead between them. To speed up execution, the RFU exploits instruction level parallelism (ILP) and spatial computation. Also, the proposed integration of the RFU efficiently exploits the pipeline structure of the processor, leading to further performance improvements. Furthermore, a development framework for the introduced architecture is presented. The framework is fully automated, hiding all reconfigurable hardware related issues from the user. The hardware model of the architecture was synthesized in a 0.13 µm process and all information regarding area and delay were estimated and presented. A set of benchmarks is used to evaluate the architecture and the development framework. Experimental results prove performance improvements i...
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e70f0c3be2caae56f9ccf8eff67bf13f https://doi.org/10.1080/00207210600565127 Zobrazit plný text záznamu