A 4-Element 800MHz-BW 29mW True-Time-Delay Spatial Signal Processor Enabling Fast Beam-Training with Data Communications
| Autor: | Subhanshu Gupta, Danijela Cabric, Veljko Boljanovic, Han Yan, Chung-Ching Lin, Deukhyoun Heo, Chase Puglisi, Soumen Mohapatra, Erfan Ghaderi |
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| Rok vydání: | 2021 |
| Předmět: |
Beamforming
Signal Processing (eess.SP) Digital signal processor Computer science Bandwidth (signal processing) Latency (audio) Systems and Control (eess.SY) True time delay Signal Electrical Engineering and Systems Science - Systems and Control Integrator Electronic engineering FOS: Electrical engineering electronic engineering information engineering Wideband Electrical Engineering and Systems Science - Signal Processing |
| Zdroj: | ESSCIRC |
| DOI: | 10.48550/arxiv.2106.01255 |
| Popis: | Spatial signal processors (SSP) for emerging millimeter-wave wireless networks are critically dependent on link discovery. To avoid loss in communication, mobile devices need to locate narrow directional beams with millisecond latency. In this work, we demonstrate a true-time-delay (TTD) array with digitally reconfigurable delay elements enabling both fast beam-training at the receiver with wideband data communications. In beam-training mode, large delay-bandwidth products are implemented to accelerate beam training using frequency-dependent probing beams. In data communications mode, precise beam alignment is achieved to mitigate spatial effects during beam-forming for wideband signals. The 4-element switched-capacitor based time-interleaved array uses a compact closed-loop integrator for signal combining with the delay compensation implemented in the clock domain to achieve high precision and large delay range. Prototyped in TSMC 65nm CMOS, the TTD SSP successfully demonstrates unique frequency-to-angle mapping with 3.8ns maximum delay and 800MHz bandwidth in the beam-training mode. In the data communications mode, nearly 12dB uniform beamforming gain is achieved from 80MHz to 800MHz. The TTD SSP consumes 29mW at 1V supply achieving 122MB/s with 16-QAM at 9.8% EVM. Comment: to be presented at the IEEE European Solid-State Circuits Conference in September 2021 |
| Databáze: | OpenAIRE |
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