High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications

Autor: Enrico Zanoni, Sven Besendörfer, Idriss Abid, Gaudenzio Meneghesso, Farid Medjdoub, Stefan Degroote, Riad Kabouche, Joff Derluyn, Elke Meissner, Roland Püsche, Marianne Germain, Matteo Meneghini, Alaleh Tajalli
Přispěvatelé: University of Padova [Padova, Italy], Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF), PCMP CHOP, Renatech Network, European Project: 720527,H2020,H2020-NMBP-2016-two-stage,InRel-NPower(2017), Università degli Studi di Padova = University of Padua (Unipd), 720527, Horizon 2020 Framework Programme, Publica
Jazyk: angličtina
Předmět:
Materials science
Silicon
Superlattice
chemistry.chemical_element
Cathodoluminescence
02 engineering and technology
Trapping
lcsh:Technology
01 natural sciences
Article
GaN
High-electron-mobility transistor (HEMT)
Trapping effect back-gating analysis
[SPI]Engineering Sciences [physics]
0103 physical sciences
Breakdown voltage
General Materials Science
lcsh:Microscopy
lcsh:QC120-168.85
Leakage (electronics)
010302 applied physics
high-electron-mobility transistor (HEMT)
lcsh:QH201-278.5
lcsh:T
business.industry
High voltage
Heterojunction
021001 nanoscience & nanotechnology
chemistry
lcsh:TA1-2040
trapping effect back-gating analysis
Optoelectronics
lcsh:Descriptive and experimental mechanics
lcsh:Electrical engineering. Electronics. Nuclear engineering
lcsh:Engineering (General). Civil engineering (General)
0210 nano-technology
business
lcsh:TK1-9971
Zdroj: Materials
Volume 13
Issue 19
Materials, MDPI, 2020, 13 (19), pp.4271. ⟨10.3390/ma13194271⟩
Materials, Vol 13, Iss 4271, p 4271 (2020)
Materials, 2020, 13 (19), pp.4271. ⟨10.3390/ma13194271⟩
ISSN: 1996-1944
DOI: 10.3390/ma13194271
Popis: The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a step-graded (SG) buffer (reference structure), and another based on a superlattice (SL). In particular, we show that: (i) the use of an SL allows us to push the vertical breakdown voltage above 1500 V on a 5 µ
m stack, with a simultaneous decrease in vertical leakage current, as compared to the reference GaN-based epi-structure using a thicker buffer thickness. This is ascribed to the better strain relaxation, as confirmed by X-Ray Diffraction data, and to a lower clustering of dislocations, as confirmed by Defect Selective Etching and Cathodoluminescence mappings. (ii) SL-based samples have significantly lower buffer trapping, as confirmed by substrate ramp measurements. (iii) Backgating transient analysis indicated that traps are located below the two-dimensional electron gas, and are related to CN defects. (iv) The signature of these traps is significantly reduced on devices with SL. This can be explained by the lower vertical leakage (filling of acceptors via electron injection) or by the slightly lower incorporation of C in the SL buffer, due to the slower growth process. SL-based buffers therefore represent a viable solution for the fabrication of high voltage GaN transistors on silicon substrate, and for the simultaneous reduction of trapping processes.
Databáze: OpenAIRE
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