3.5-D integration: A case study
| Autor: | Pierre-Emmanuel Gaillardon, Vasilis F. Pavlidis, Giovanni De Micheli, Ciprian Seiculescu, Shashikanth Bobba |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
010302 applied physics
Interconnection Engineering business.industry Three-dimensional integrated circuit 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY MPSoC 01 natural sciences Vertical integration Manufacturing cost 020202 computer hardware & architecture Network on a chip Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS Performance improvement business Activity-based costing |
| Zdroj: | ISCAS |
| DOI: | 10.1109/ISCAS.2013.6572285 |
| Popis: | Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration scheme that combines these two approaches, taking into account their existing technology limits, into a disruptive paradigm called 3.5-D integration. Our novel integration supports circuit-partitioning both at the gate and block level with unprecedented benefits in cost. To demonstrate the effectiveness of 3.5-D integration, we chose as case study a 288-core MPSoC and we made hypothesis on the manufacturing and test cost. We argue a potential 20% decrease in the manufacturing cost and 30% decrease in the test cost when compared to 3-D TSV integration. In order to study the performance improvement of the MPSoC, we benchmarked various blocks of the core and the on-chip interconnection network, connecting all the cores. Our study shows large improvement in performance of the core (average of 11.5%) and latency (average of 24%) of the Network-on-Chip (NoC) for the 3.5-D integration when compared to the corresponding 3-D TSV implementation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|