A low-power high storage capacity structure for GaAs MESFET ROM
| Autor: | A. Guyot, B. Hochet, R. Kanan, M. Declercq |
|---|---|
| Přispěvatelé: | Electronics Laboratory (SWISS FEDERAL INSTITUTE OF TECHNOLOGY), Ecole Polytechnique Fédérale de Lausanne (EPFL), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), EINEV - Ecole d'Ingénieurs de l'Etat de Vaud (EINEV), Ecole d'Ingénieurs de l'Etat de Vaud, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 1997 |
| Předmět: |
noise-margin
Engineering access-time storage-capacity subthreshold-currents 02 engineering and technology Integrated circuit design leakage-currents 01 natural sciences Gallium arsenide chemistry.chemical_compound 0.6-micron 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Leakage (electronics) 010302 applied physics low-power-operation business.industry Subthreshold conduction 8-Kbit 020208 electrical & electronic engineering Electrical engineering MESFET-ROM 60-mW Dissipation Noise margin divided-decoder-matrix 1.2-ns chemistry DCFL-gate PACS 85.42 MESFET GaAs business Access time power-dissipation |
| Zdroj: | Proceedings.-International-Workshop-on-Memory-Technology,-Design-and-Testing-Cat.-No.97TB100159. Proceedings.-International-Workshop-on-Memory-Technology,-Design-and-Testing-Cat.-No.97TB100159., 1997, San Jose, CA, United States. pp.58-63, ⟨10.1109/MTDT.1997.619396⟩ |
| DOI: | 10.1109/MTDT.1997.619396⟩ |
| Popis: | ISBN: 0818680997; Gallium Arsenide (GaAs) is used in the design of high speed systems; however, it is difficult or impossible to realize high-capacity ROMs, because of subthreshold currents and an unacceptable power dissipation. This paper describes a new approach which overcomes the above problems and allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. In addition, this approach improves the noise margin of the DCFL gate with the increase of the fan-in. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 mu m-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW. |
| Databáze: | OpenAIRE |
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