Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology
| Autor: | Alexandra L. Zimpeck, Leonardo H. Brendler, Cristina Meinhardt, Ricardo Reis |
|---|---|
| Přispěvatelé: | Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), ONERA / DPHY, Université de Toulouse [Toulouse], PRES Université de Toulouse-ONERA, Universidade Federal de Santa Catarina = Federal University of Santa Catarina [Florianópolis] (UFSC), ONERA-PRES Université de Toulouse |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Computer science
02 engineering and technology Network topology law.invention [SPI]Engineering Sciences [physics] law Robustness (computer science) 0202 electrical engineering electronic engineering information engineering Microelectronics MICROELECTRONICS Electrical and Electronic Engineering [PHYS]Physics [physics] business.industry FINFET TECHNOLOGY 020208 electrical & electronic engineering Transistor RADIATION EFFECTS Logic level PROCESS VARIABILITY Sizing Reliability engineering Logic synthesis Logic gate RELIABILITY business Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2020, 67 (2), pp.553-564. ⟨10.1109/TCSI.2019.2927374⟩ |
| ISSN: | 1549-8328 1558-0806 |
| DOI: | 10.1109/TCSI.2019.2927374⟩ |
| Popis: | International audience; Transistor arrangement influences the performance of logic cells. Complex logic cells can be used to minimize area, delay, and power. However, with the increasing relevance of nanometer challenges such as process variability and radiation effects, it is also necessary to consider these factors at logic level design. The main contribution of this work is to evaluate the advantages of adopting a multi-level logic design instead of using complex gates to mitigate process variability and radiation effects. A justification for choosing the parameter that will characterize process variability is presented. Also, the analysis with different transistor arrangements and sizing is carried out to provide a basis for a better understanding of the obtained results. The experimental evaluation considers two topologies: complex gates and multi-level using basic gates, for a set of logic gates using the 7nm FinFET technology at the layout level. As expected, at nominal conditions, the best choice is to adopt complex gate topology to optimize area, power consumption, and performance. However, the logic multi-level arrangements became the functions up to 50% less sensitive to the transient faults and at least 30% more robust to the process variability effects. A trade-off needs to be done, considering the area and power constraints. |
| Databáze: | OpenAIRE |
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