SafeSU: an extended statistics unit for multicore timing interference
| Autor: | Guillem Cabo, Ruben Lorenzo, Miquel Moreto, David Trilla, Jaume Abella, Sergi Alcaide, Francisco Bas, Carles Hernandez |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
Controllability
Multi-core processor Observability Computer science Real-time data processing Multiprocessadors MPSoC Commercialization Unit (housing) Interference (communication) Statistics Multiprocessors Safety Realization (systems) Temps real (Informàtica) Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) 2021 IEEE European Test Symposium (ETS) ETS |
| Popis: | Statistics units (SUs) in MPSoCs are becoming increasingly used for the (1) verification and (2) validation of multicore timing interference, as well as for (3) deploying safety measures in safety-related real-time systems. However, existing SU extensions to manage multicore timing interference have neither been integrated together nor deployed in commercial MPSoCs.This paper presents the realization of the Safe Statistics Unit (SafeSU for short), which smartly integrates existing solutions for multicore timing interference verification, validation and monitoring, and is in turn integrated in commercial space-graded RISC-V and SparcV8 MPSoCs. Our evaluation illustrates the operation of the SafeSU, and paves the way for a thorough validation prior to reaching commercialization and being offered as open source IP. This work has received funding from the European Union’s Horizon 2020 Research and Innovation programme under Grant Agreement EICFTI 869945. |
| Databáze: | OpenAIRE |
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