Using binary decision diagrams to speed up the test pattern generation of behavioral circuit descriptions written in hardware description languages

Autor: J.-F. Santucci, L. Vandeventer
Přispěvatelé: EERIE, IMT - MINES ALES (IMT - MINES ALES), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Sciences pour l'environnement (SPE), Centre National de la Recherche Scientifique (CNRS)-Université Pascal Paoli (UPP), IEEE
Rok vydání: 2002
Předmět:
Zdroj: ISCAS
Proceedings of the IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94
IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94
IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94, 1994, London, United Kingdom. pp.279-282, ⟨10.1109/ISCAS.1994.408809⟩
ISSN: 7803-1915
DOI: 10.1109/iscas.1994.408809
Popis: ISBN: 0-7803-1915-X website : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=9169&arnumber=408809&count=123&index=69; International audience; In this paper, we focus on test pattern generation for circuit descriptions written in hardware description languages according to the circuit behavior. We develop an algorithmic improvement method which is devoted to speed up the deterministic and fault-oriented test systems which deal with such circuit descriptions. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach
Databáze: OpenAIRE