The use of SystemC for design verification and integration test of IP-cores
Autor: | D. Signoretto, Franco Fummi, Alessandro Fin |
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Rok vydání: | 2002 |
Předmět: |
Computer science
business.industry Hardware description language Codesign Abstraction layer Embedded software Application-specific integrated circuit Computer architecture SystemC Embedded system Server VHDL IPCore business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Formal verification computer computer.programming_language |
Zdroj: | Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558). |
DOI: | 10.1109/asic.2001.954676 |
Popis: | The current trend of systems on silicon is leading to System-on-Chips with embedded software and hardware components. Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. The SystemC language allows one to create and integrate accurate models of software algorithms, hardware architectures and interfaces for SoCs. In this paper, characteristics of the language are exploited to define a design verification framework for integration-test of IP-cores. Intellectual property of cores is guaranteed by adopting-a client/server simulation architecture and by allowing functional test generation on faulty IP-core models without disclosing their internal structure. Moreover, the methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC. |
Databáze: | OpenAIRE |
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