Path resizing based on incremental technique
Autor: | Nadine Azemard, Daniel Auvergne, S. Cremoux |
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Přispěvatelé: | Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Conception et Test de Systèmes MICroélectroniques (SysMIC), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
Rok vydání: | 2002 |
Předmět: |
Mathematical optimization
Computer science business.industry 020208 electrical & electronic engineering 02 engineering and technology Integrated circuit layout Circuit extraction 020202 computer hardware & architecture Design layout record Path (graph theory) 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Electronic engineering Local search (optimization) [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Physical design business IC layout editor Hardware_LOGICDESIGN Electronic circuit |
Zdroj: | International Symposium on Circuits and Systems ISCAS: International Symposium on Circuits and Systems ISCAS: International Symposium on Circuits and Systems, May 1998, Monterey, CA, United States. pp.90-93, ⟨10.1109/ISCAS.1998.705219⟩ |
DOI: | 10.1109/iscas.1998.705219 |
Popis: | International audience; Based on an incremental path search algorithm, this paper addresses the problem of longest combinational paths selection for performance optimization at physical level. A realistic evaluation of gate delay and controlled sizing techniques are used to manage the circuit path sizing alternatives, such as delay or power/area constraints. The efficiency of this technique is demonstrated and also illustrated on several ISCAS'85 benchmark circuits. A comparison is given between regular sizing alternatives to local optimization steps controlled by specific indicators. |
Databáze: | OpenAIRE |
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