Power balanced gates insensitive to routing capacitance mismatch

Autor:	Alexander Taubin, Zhen Wang, Konrad J. Kulikowski, Vyas Venkataraman
Rok vydání:	2008
Předmět:	Interconnection Computer science Logic gate Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Capacitance Electronic circuit
Zdroj:	DATE
DOI:	10.1145/1403375.1403685
Popis:	Cryptographic hardware is vulnerable to power analysis attacks. To resist these attacks, special balanced dual-rail gates have been developed which have equal power consumption for all valid data values and transitions. A limitation of existing designs is that they require balanced routing of the dual-rail interconnect between gates. Natural process variation and suboptimal routing tools make it practically impossible to perfectly match the capacitances of the dual-rail pair making the balanced routing constraint difficult to satisfy. We present a general method and designs which achieve power balance in dual-rail circuits without requiring matching of gate output load capacitances or random masking. The method and design are based on a directional discharge protocol which ensures that both rails are always fully discharged and charged in each cycle.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d9bc2f14154ac831282c22d7ec72cad9 https://doi.org/10.1145/1403375.1403685 Zobrazit plný text záznamu