Case study: deployment of the 2D NoC on 3D for the generation of large emulation platforms
| Autor: | Junyan Tan, Virginie Fresse, Zhiwei Ge, Frederic Rousseau |
|---|---|
| Přispěvatelé: | Laboratoire Hubert Curien [Saint Etienne] (LHC), Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS)-Institut d'Optique Graduate School (IOGS), ASIC Design Center (ASIC Design Center), University of tianjin, Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), projet Semba, Cluster 2, Institut d'Optique Graduate School (IOGS)-Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2012 |
| Předmět: |
Engineering
Computer science multi-component Design flow 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY Hermes NoC 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS Field-programmable gate array 020203 distributed computing Emulation business.industry 020208 electrical & electronic engineering emulation platform Hardware emulation 020202 computer hardware & architecture IEEE Logic synthesis Network on a chip Computer architecture Software deployment Embedded system [INFO.INFO-ES]Computer Science [cs]/Embedded Systems Performance improvement business NoC 3D |
| Zdroj: | IEEE International Symposium on Rapid System Prototyping IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland. 7 p RSP IPTA |
| Popis: | International audience; The evaluation of Network-On-Chip (NoC) architectures is an up to date problem in the design of System-on-Chip. Emulation on FPGA (Field Programmable Gate Array) is used to cover all possible NoC solutions in a reduced exploration time. Emulation requires multi-FPGA platform as the resources for large NoC is important and cannot be handling by one FPGA. In the same time, SoC community is exploring 3D technology for the next generation of large SoC with 3D NoC, making emulation more complex. This paper presents a case study of the deployment of the 2D NoC structure to 3D. A design flow is proposed for the automatic generation of a NoC targeting3D on multi-FPGAs. The flow integrates emulation blocks used for the validation and exploration on the NoC. With this automatic aided tool, the designer can evaluate and explore the NoC architecture and extract performances of the NoC regardless of the multi-component platform. One may expect a communication performance improvement using an adapted partitioning of the NoC, as highlighted by the results given in this paper. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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