Design and implementation of the POWER5/spl trade/ microprocessor
| Autor: | J. Dawson, Mike Lee, S. Dodson, Phillip J. Restle, Balaram Sinharoy, G. Gorman, N. Schwartz, Steve Runyon, Ronald Nick Kalla, Joachim Gerhard Clabes, M. Goulet, Jack DiLullo, J. Wagoner, Mark D. Sweet, L. Powell, Paul H. Muench, J. McGill, Donald W. Plass, Michael Stephen Floyd, Joshua Friedrich, Sam Gat-Shang Chu |
|---|---|
| Rok vydání: | 2004 |
| Předmět: |
Power management
Engineering Serviceability (computer) POWER5 business.industry Computer science Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design ComputerSystemsOrganization_PROCESSORARCHITECTURES Simultaneous multithreading CAS latency law.invention Microprocessor Application-specific integrated circuit law Embedded system Multithreading Hardware_INTEGRATEDCIRCUITS Execution unit Physical design IBM business |
| Zdroj: | 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866). |
| DOI: | 10.1109/icicdt.2004.1309931 |
| Popis: | POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5's dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip's frequency, area, power, and thermal targets. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|