A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications
| Autor: | Keum Cheol Hwang, YoungGun Pu, Kang-Yoon Lee, Qurat Ul Ain, Youngoo Yang, Khuram Shehzad, SungJin Kim, Minjae Lee, Deeksha Verma, Dongsoo Lee, Danial Khan |
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| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
General Computer Science
Comparator capacitive DAC (CDAC) Computer science 02 engineering and technology 01 natural sciences law.invention Bluetooth low energy (BLE) Sampling (signal processing) law IEEE 802.15.1 IoT sensors 0202 electrical engineering electronic engineering information engineering Electronic engineering General Materials Science Power semiconductor device Common-mode signal low power consumption IEEE 802.15 020208 electrical & electronic engineering 010401 analytical chemistry General Engineering Successive approximation ADC Adaptive power control (APC) 0104 chemical sciences asynchronous logic Capacitor Effective number of bits CMOS Asynchronous communication lcsh:Electrical engineering. Electronics. Nuclear engineering lcsh:TK1-9971 Asynchronous circuit Power control |
| Zdroj: | IEEE Access, Vol 8, Pp 85869-85879 (2020) |
| ISSN: | 2169-3536 |
| Popis: | An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (VCM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is $45~\mu \text{W}$ when operated at 1 V power supply. |
| Databáze: | OpenAIRE |
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