SEU tolerant memory design for the ATLAS pixel readout chip
| Autor: | A. Mekkaoui, Alexandre Rozanov, R. Beccherle, Y. Lu, V. Gromov, J. Fleury, Mohsine Menouni, Marlon Barbero, Dario Gnani, J.D. Schipper, V. Zivkovic, F. Jensen, Lea Caminada, Malte Backhaus, F. Gensolen, M Garcia-Sciveres, Tomasz Hemperek, Laura Gonella, M. Karagounis, Giovanni Darbo, R. Kluit, D. Fougeron, Sourabh Dube, Hans Krueger, P. Breugnon, Andre Kruth, D. Arutinov |
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| Přispěvatelé: | Centre de Physique des Particules de Marseille (CPPM), Aix Marseille Université (AMU)-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: |
Computer science
Dice Hardware_PERFORMANCEANDRELIABILITY Microelectronics and interconnection technology [3] 01 natural sciences Atlas (anatomy) Front-end electronics for detector readout 0103 physical sciences medicine [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Detectors and Experimental Techniques 010306 general physics 29.40.Gx Tracking and position-sensitive detectors 85.30.Tv Field effect devices Instrumentation Mathematical Physics Radiation-hard electronics Shareable IP Blocks for HEP [3.3] Hardware_MEMORYSTRUCTURES Pixel 010308 nuclear & particles physics business.industry Radiation damage to electronic components Electrical engineering Chip Upgrade medicine.anatomical_structure Analogue electronic circuits business Cmos process Computer hardware |
| Zdroj: | JINST, (2013) pp. C02026 Journal of Instrumentation Topical Workshop on Electronics for Particle Physics 2012 (TWEPP12) Topical Workshop on Electronics for Particle Physics 2012 (TWEPP12), Sep 2012, Oxford, United Kingdom. pp.C02026, ⟨10.1088/1748-0221/8/02/C02026⟩ |
| Popis: | International audience; The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented. |
| Databáze: | OpenAIRE |
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