An Adaptive-Resolution Quasi-Level-Crossing-Sampling ADC Based on Residue Quantization in 28-nm CMOS
| Autor: | Marek Miskowicz, Robert Bogdan Staszewski, Hongying Wang, Filippo Schembari |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Physics
Quantization (signal processing) 020208 electrical & electronic engineering 020206 networking & telecommunications Successive approximation ADC 02 engineering and technology law.invention Capacitor CMOS Asynchronous communication law Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Data transmission Voltage |
| Zdroj: | IEEE Solid-State Circuits Letters |
| ISSN: | 2573-9603 |
| Popis: | We present a digitally intensive adaptive-resolution (AR) quasi-level-crossing-sampling (quasi-LCS) analog-to-digital converter (ADC) for Internet-of-Things wireless networks, where the power consumed in data transmission, processing, and storage can be significantly reduced by minimizing the ADC’s gross output bit-rate. The AR quasi-LCS ADC is implemented as a delta-modulator and adopts a 4-bit asynchronous SAR ADC to quantize the residue voltage signal, thus allowing a straightforward implementation of LCS and AR algorithms in the digital domain, as well as yielding a digital-friendly architecture. Fabricated in 28-nm CMOS, this ADC achieves an SNDR of 53 dB over 1.42 MHz signal bandwidth while consuming 205 $\mu \text{W}$ and an active area of 0.0126 mm2. |
| Databáze: | OpenAIRE |
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