Regular expression based test sequence generation for HDL program validation

Autor: Onur Kilinccceker, Moharram Challenger, Ercument Turk, Fevzi Belli
Přispěvatelé: MÜ, TR125949, Belli, Fevzi, Izmir Institute of Technology. Computer Engineering
Jazyk: angličtina
Rok vydání: 2018
Předmět:
Zdroj: 2018 IEEE International Conference on Software Quality, Reliability and Security Companion (QRS-C), 16-20 July, 2018, Lisbon, Portugal
QRS Companion
Popis: 18th IEEE International Conference on Software Quality, Reliability, and Security Companion, QRS-C 2018; Lisbon; Portugal; 16 July 2018 through 20 July 2018
This paper proposes a test sequence generation approach for behavioral model validation of sequential circuits implemented in Hardware Description Language (HDL). In the procedure of test sequence generation proposed in this study, Regular Expressions (REs) are utilized to model the behavior of the System Under Test (SUT). First, the HDL program is converted to a Finite State Machine (FSM). Then, the obtained FSM is transformed to RE which is represented by a Syntax Tree (ST). In this way, the test sequence generation problem is simplified to the tree traversal algorithm in which symbol and operator coverage criteria are satisfied. The required tools for test sequence generation are provided to automatize the whole procedure of the proposed approach. Also, a running example, based on a real-life-like Traffic Light Controller (TLC), validates the proposed approach and analyzes its characteristic features.
Databáze: OpenAIRE