Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core
| Autor: | Gabor, Ron, Sazeides, Yiannakis, Bramnik, Arkady, Andreou, Alexandros, Nicopoulos, Chrysostomos, Patsidis, Karyofyllis, Konstantinou, Dimitris, Dimitrakopoulos, Giorgos |
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| Přispěvatelé: | Nicopoulos, Chrysostomos [0000-0001-6389-6068], Patsidis, Karyofyllis [0000-0002-4638-1828], Dimitrakopoulos, Giorgos [0000-0003-3688-7865] |
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Out-of-order execution business.industry Computer science Embedded system Reliability (computer networking) 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Register renaming 02 engineering and technology business 01 natural sciences 020202 computer hardware & architecture |
| Zdroj: | 2019 Design, Automation Test in Europe Conference Exhibition (DATE) DATE |
| Popis: | Emerging mission-critical and functional safety applications require high-performance processors that meet strict reliability requirements against random hardware failures. These requirements touch even sub-systems within the core that, so far, may have been considered as low-significance contributors to the processor failure rate. This paper identifies the register renaming sub-system of an out-of-order core as a prime example of where cost-efficient and non-intrusive protection can enable future processors to meet their reliability goals. We propose two hardware schemes that guard against failures in the register renaming sub-system of a core: a technique for the detection of random hardware errors in the physical register identifiers, and a method to recover from the detected errors. 812 817 |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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