(Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates
| Autor: | Simoen, E., Hsu, P. C., Takakura, K., Syshchyk, O., Vais, A., Yu, H., Parvais, B., Collaert, N., Claeys, C. |
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| Přispěvatelé: | Simoen, E., Kononchuk, O., Nakatsuka, O., Claeys, C., Physics, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics |
| Rok vydání: | 2021 |
| Předmět: | |
| Zdroj: | ECS Transactions. 102:53-62 |
| ISSN: | 1938-6737 1938-5862 |
| DOI: | 10.1149/10204.0053ecst |
| Popis: | Optimization of heterogeneous epitaxial techniques such as aspect ratio trapping and nano-ridge engineering strongly triggered the commercial breakthrough of III-V on Si devices for a variety of applications in fields like optoelectronics, lighting, telecommunication, power devices, RF circuitry etc. To achieve high device performance defect engineering is crucial to avoid increased leakage current, lifetime degradation and/or increased low frequency noise. The aim of this review is to discuss the present understanding of defects in III-V materials and devices and their impact on the device performance. This is illustrated by analyzing three important types of devices, including InxGa1-xAs p+n diodes, GaN/AlGaN/Si transistors (MOSFETs, HEMTs and MOSHEMTs) and GaAs/InGaP Heterojunction Bipolar Transistors (HBTs). It will be pointed out that by an appropriate defect control the further development of the monolithic III-V integration on Si will not be hampered and is facing a bright future. |
| Databáze: | OpenAIRE |
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