A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines
| Autor: | N. St. John, S. Mandal, S. Miryala, P. Maj, G.W. Deptuch, E. Raguzin, S. Rescia |
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| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: |
Signal Processing (eess.SP)
FOS: Computer and information sciences Hardware Architecture (cs.AR) FOS: Electrical engineering electronic engineering information engineering Electrical Engineering and Systems Science - Signal Processing Computer Science - Hardware Architecture Instrumentation Mathematical Physics |
| Popis: | A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s. Submitted to JINST |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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