Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET
| Autor: | Khaled Shehata, Hani Ragai, Hanady H. Issa, Amin A. Zayed |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Hardware security module
General Computer Science Comparator Computer science Physical unclonable function 02 engineering and technology Reduction (complexity) Reliability (semiconductor) transient effect of ring oscillator 0202 electrical engineering electronic engineering information engineering Electronic engineering General Materials Science low power consumption process variation Authentication reliability 020208 electrical & electronic engineering General Engineering 020202 computer hardware & architecture Power (physics) ComputingMilieux_MANAGEMENTOFCOMPUTINGANDINFORMATIONSYSTEMS Logic gate hardware security lcsh:Electrical engineering. Electronics. Nuclear engineering lcsh:TK1-9971 Voltage |
| Zdroj: | IEEE Access, Vol 9, Pp 27696-27707 (2021) |
| ISSN: | 2169-3536 |
| DOI: | 10.1109/access.2021.3058678 |
| Popis: | The main purpose of this paper is to achieve ultra-low power Physical Unclonable Function (PUF) to meet the requirements for Internet of Things (IoT) applications. PUFs are promising hardware security primitives that are based on the uniqueness and the unclonability of the device's physical characteristics to provide a unique identifier for devices. PUFs can be used in device authentication and for secure key storage and generation. This paper presents Oscillator Collapse Physical Unclonable Function (OC-PUF), which is suitable for low power applications. The power consumption is reduced based on designing the most power-hungry modules in the OC-PUF. An Oscillator Collapse (OC) is designed to work in the near-threshold voltage region, which reduces the power consumption. More power reduction is achieved by designing a new Collapse Time Comparator (CTC). Due to the process variations, the oscillations period of each OC is different. The CTC generates the output response bit by comparing the oscillations periods of the two selected OCs. The simulation results demonstrate that the proposed OC-PUF can effectively reduce the power consumption. The proposed PUF is designed using 20 nm triple gate FinFET technology. The Simulation results for 1000 different chips with the same input challenge, show that the average power is 140 nW, with the worst case being 740 nW. The best case is 63 nW per challenge-response pair at supply voltage 0.5 V. The averaged reliability of the OC-PUF is 99.8%, at temperatures from -40 to 125 °C and supply voltage 0.5 ± 10%. The proposed OC-PUF decreases the power consumption while retaining high-performance metrics. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|