Performance and power of cache-based reconfigurable computing
| Autor: | Ralph D. Wittig, Andrew Putnam, Susan J. Eggers, Eric F. Dellinger, Jeffrey M. Mason, Henry E. Styles, Dave Bennett, Prasanna Sundararajan |
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| Rok vydání: | 2009 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Source code Computer science business.industry media_common.quotation_subject Parallel computing Data structure computer.software_genre Reconfigurable computing Computer architecture Embedded system Memory architecture Compiler Cache Memory model business Field-programmable gate array computer Performance per watt media_common |
| Zdroj: | FPGA ISCA |
| DOI: | 10.1145/1508128.1508189 |
| Popis: | Many-cache is a memory architecture that efficiently supports caching in commercially available FPGAs. It facilitates FPGA programming for high-performance computing (HPC) developers by providing them with memory performance that is greater and power consumption that is less than their current CPU platforms, but without sacrificing their familiar, C-based programming environment.Many-cache creates multiple, multi-banked caches on top of an FGPA's small, independent memories, each targeting a particular data structure or region of memory in an application and each customized for the memory operations that access it. The caches are automatically generated from C source by the CHiMPS C-to-FPGA compiler.This paper presents the analyses and optimizations of the CHiMPS compiler that construct many-cache caches. An architectural evaluation of CHiMPS-generated FPGAs demonstrates a performance advantage of 7.8x (geometric mean) over CPU-only execution of the same source code, FPGA power usage that is on average 4.1x less, and consequently performance per watt that is also greater, by a geometric mean of 21.3x. |
| Databáze: | OpenAIRE |
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