The EDRO Board Connected to the Associative Memory: a 'Baby' FastTracKer Processor for the ATLAS Experiment
| Autor: | F. M. Giorgi, Andrea Negri, Paola Giannetti, Chiara Roda, Matteo Beretta, M. Piendibene, R. A. Vitillo, D. Magalotti, Mauro Villa, Alberto Annovi, Carla Sbarra, V. Bevacqua, F. Cervigni, G. Volpi, Laura Fabbri, Francesco Crescioli |
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| Přispěvatelé: | Annovi A., Beretta M., Bevacqua V., Cervigni F., Crescioli F., Fabbri L., Giannetti P., Giorgi F., Magalotti D., Negri A., Piendibene M., Roda C., Sbarra C., Villa M., Vitillo R. A., Volpi G. |
| Jazyk: | angličtina |
| Předmět: |
Digital electronics
Pixel business.industry Computer science Tracking ATLAS experiment Detector Physics and Astronomy(all) Content-addressable memory Vertical slice FTK Trigger concept and systems DATA ACQUISITION VERTEX DETECTOR Associative Memory Detectors and Experimental Techniques business Field-programmable gate array Cluster analysis Computer hardware FPGA |
| Zdroj: | Physics Procedia. :1772-1780 |
| ISSN: | 1875-3892 |
| DOI: | 10.1016/j.phpro.2012.02.502 |
| Popis: | The FastTracKer (FTK) is a dedicated hardware system able to perform online fast and precise track reconstruction of full events in the Atlas experiment within an average latency of a few dozen microseconds. It consists of two pipelined processors: the Associative Memory (AM), which finds low precision tracks called “roads”, and the Track Fitter (TF), which refines the track quality with high precision fits. The FTK design [1] that works well at the Large Hadron Collider (LHC) Phase I upgrade luminosity requires the best of the available technology for tracking in a high occupancy environment. While the new processor is designed for the most demanding LHC conditions, we will begin with existing prototypes, some developed for the SLIM5 collaboration [2], to exercise the FTK functions in the new Atlas environment. The goal is to learn early about the FTK integration in the Atlas TDAQ. The EDRO board (Event Dispatch and Read-Out) receives on a clustering mezzanine (able to calculate the pixel and SCT cluster centroids) simulated detector raw data on S-links from a “pseudo-front-end” (a CPU). The clusters are transferred through the P3 connector to the AM board that finds roads that in turn are sent back to the EDRO. The EDRO delivers the found roads to the CPU using an S-link connection. This system will grow to become the FTK “Vertical Slice”: the EDRO will also have the capability to send the roads and the clusters in them to the TF that will initially be the GigaFitter developed for the SVT processor at CDF [3]. Our goal is to take data before the end of the 2012 run. The vertical slice will cover a small projective tower in the detector, but it will be a demonstrator since it will be functionally complete. We report on the performance and structure of the nucleus of the vertical slice, including the pixel/strip hit clustering (clustering mezzanine), hit organization and distribution (EDRO) and the Associative Memory road-finding function. [1] A. Andreani et al., The FastTracker Real Time Processor and Its Impact on Muon Isolation, Tau and b-Jet Online Selections at ATLAS, Conference Record 17th IEEE NPSS Real Time Conference Record of the 17th Real Time Conference, Lisbon, Portugal, 24 - 28 May 2010. [2] S. Bettarini et al., The SLIM5 low mass silicon tracker demonstrator, Nuclear Instruments and Methods in Physics Research A 623 (2010) 942–953 [3] S. Amerio et al., GigaFitter: Performance at CDF and perspective for future applications, Nuclear Instruments and Methods in Physics Research A 623(2010)540–542 |
| Databáze: | OpenAIRE |
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