Static energy reduction techniques for microprocessor caches
| Autor: | Stephen W. Keckler, M. S. Hrishikesh, Heather Lynn Hanson, Vikas Agarwal, Doug Burger |
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| Rok vydání: | 2003 |
| Předmět: | |
| Zdroj: | ICCD |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2003.812370 |
| Popis: | Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption due to sub-threshold leakage current. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching can be used to turn off the memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places the memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy/performance trade-offs of these techniques and find that the dynamic threshold modulation achieves the best results for level-1 caches, improving the energy-delay product by 2% in a level-1 instruction cache and 7% in a level-1 data cache. Low-leakage transistors perform best for the level-2 cache as they reduce the static energy by up to 98% and improve the energy-delay product by more than a factor of 50. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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