DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
| Autor: | Guillem Cabo, Gerard Candon, Xavier Carril, Max Doblas, Marc Dominguez, Alberto Gonzalez, Cesar Hernandez, Victor Jimenez, Vatistas Kostalampros, Ruben Langarita, Neiel Leyva, Guillem Lopez-Paradis, Jonnatan Mendoza, Francesco Minervini, Julian Pavon, Cristobal Ramirez, Narcis Rodas, Enrico Reggiani, Mario Rodriguez, Carlos Rojas, Abraham Ruiz, Victor Soria, Alejandro Suanes, Ivan Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Victor Montabes, Adrian Cristal, Carles Hernandez, Ricardo Martinez, Miquel Moreto, Francesc Moll, Oscar Palomar, Marco A. Ramirez, Antonio Rubio, Jordi Sacristan, Francesc Serra-Graells, Nehir Sonmez, Lluis Teres, Osman Unsal, Mateo Valero, Luis Villa |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. EFRICS - Efficient and Robust Integrated Circuits and Systems |
| Rok vydání: | 2022 |
| Předmět: |
Microprocessor chips
Logic design Reduced instruction set computing RISC-V Vector processor Phase locked loops Vector processor systems Microprocessadors -- Disseny i construcció Analogue-digital conversion CMOS integrated circuits Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Microprocessors -- Design and construction |
| Zdroj: | 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS). |
| Popis: | This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology. The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN). Peer Reviewed Article signat per 43 autors/es: Guillem Cabo∗, Gerard Candón∗, Xavier Carril∗, Max Doblas∗, Marc Domínguez∗, Alberto González∗, Cesar Hernández†, Víctor Jiménez∗, Vatistas Kostalampros∗, Rubén Langarita∗, Neiel Leyva†, Guillem López-Paradís∗, Jonnatan Mendoza∗, Francesco Minervini∗, Julian Pavón∗, Cristobal Ramírez∗, Narcís Rodas∗, Enrico Reggiani∗, Mario Rodríguez∗, Carlos Rojas∗, Abraham Ruiz∗, Víctor Soria∗, Alejandro Suanes‡, Iván Vargas∗, Roger Figueras∗, Pau Fontova∗, Joan Marimon∗, Víctor Montabes∗, Adrián Cristal∗, Carles Hernández∗, Ricardo Martínez‡, Miquel Moretó∗§, Francesc Moll∗§, Oscar Palomar∗§, Marco A. Ramírez†, Antonio Rubio§, Jordi Sacristán‡, Francesc Serra-Graells‡, Nehir Sonmez∗, Lluís Terés‡, Osman Unsal∗, Mateo Valero∗§, Luís Villa† // ∗Barcelona Supercomputing Center (BSC), Barcelona, Spain. Email: name.surname@bsc.es; †Centro de Investigación en Computación, Instituto Politécnico Nacional (CIC-IPN), Mexico City, Mexico; ‡ Institut de Microelectronica de Barcelona, IMB-CNM (CSIC), Spain. Email: name.surname@imb-cnm.csic.es; §Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. Email: name.surname@upc.edu |
| Databáze: | OpenAIRE |
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