800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology
| Autor: | Roland Schuetz, David Chinn, Jin-Ki Kim, Peter B. Gillingham, Hakjune Oh, Don Macdonald, Hong-Beom Pyeon, Eric T. Choi |
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| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
General Computer Science nonvolatile memory business.industry Computer science Nand flash memory General Engineering Source-synchronous NAND gate Ring network Chip high speed integrated circuits Phase-locked loop Low-power electronics Disk drives General Materials Science Integrated circuit packaging lcsh:Electrical engineering. Electronics. Nuclear engineering Double data rate business lcsh:TK1-9971 Computer hardware |
| Zdroj: | IEEE Access, Vol 1, Pp 811-816 (2013) |
| ISSN: | 2169-3536 |
| Popis: | A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wide point-to-point source-synchronous double data-rate (DDR) interface for low power 800 MB/s operation in a ring topology. Interface power is reduced by shutting down the phase-locked loop in every second MCP and alternating between edge aligned DDR clock and center aligned DDR clock for source-synchronous data transfer from MCP to MCP. |
| Databáze: | OpenAIRE |
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