Memory Reliability Improvement Based on Maximized Error-Correcting Codes
| Autor: | Yannick Bonhomme, Samuel Evain, Valentin Gherman |
|---|---|
| Přispěvatelé: | Département d'Architectures, Conception et Logiciels Embarqués-LIST (DACLE-LIST), Laboratoire d'Intégration des Systèmes et des Technologies (LIST), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-10-SEGI-0007,EMYR,Rendement et Fiabilité des Mémoires en technologie MRAM(2010), Laboratoire d'Intégration des Systèmes et des Technologies (LIST (CEA)) |
| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: |
Independent and identically distributed random variables
Mean time between failures Magnetoresistive random-access memory 021103 operations research Data interface Computer science Resistance-switching memory 0211 other engineering and technologies Code word 02 engineering and technology MRAM Reliability SEC 020202 computer hardware & architecture [SPI]Engineering Sciences [physics] MTTF 0202 electrical engineering electronic engineering information engineering Error correcting ECC Electrical and Electronic Engineering Latency (engineering) Hardware_ARITHMETICANDLOGICSTRUCTURES Error detection and correction Algorithm DEC |
| Zdroj: | Journal of Electronic Testing Journal of Electronic Testing, Springer Verlag, 2013, 29, pp.601-608. ⟨10.1007/s10836-013-5396-6⟩ Journal of Electronic Testing: : Theory and Applications Journal of Electronic Testing: : Theory and Applications, 2013, 29, pp.601-608. ⟨10.1007/s10836-013-5396-6⟩ |
| ISSN: | 0923-8174 1573-0727 |
| DOI: | 10.1007/s10836-013-5396-6⟩ |
| Popis: | International audience; Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable. |
| Databáze: | OpenAIRE |
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