Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

Autor: Walter Riess, M. Najmzadeh, Adrian M. Ionescu, K. Boucart
Rok vydání: 2010
Předmět:
Zdroj: Solid-State Electronics. 54:935-941
ISSN: 0038-1101
DOI: 10.1016/j.sse.2010.04.037
Popis: This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/Ioff characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4–5 GPa peak of lateral uniaxial tensile stress in the Si NW.
Databáze: OpenAIRE