Automated Functional Verification of Application Specific Instruction-set Processors
| Autor: | Marcela Šimková, Zdeněk Kotásek, Tomáš Hruška, Zdeněk Přikryl |
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| Přispěvatelé: | Brno University of Technology [Brno] (BUT), Gunar Schirner, Marcelo Götz, Achim Rettberg, Mauro C. Zanella, Franz J. Rammig, TC 10 |
| Rok vydání: | 2013 |
| Předmět: |
High-level verification
Functional verification business.industry Computer science media_common.quotation_subject 020208 electrical & electronic engineering 02 engineering and technology SystemVerilog 020202 computer hardware & architecture Task (project management) Instruction set Embedded system New product development 0202 electrical engineering electronic engineering information engineering [INFO]Computer Science [cs] Quality (business) Electronics business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer computer.programming_language media_common |
| Zdroj: | IFIP Advances in Information and Communication Technology ISBN: 9783642388521 IESS IFIP Advances in Information and Communication Technology 4th International Embedded Systems Symposium (IESS) 4th International Embedded Systems Symposium (IESS), Jun 2013, Paderborn, Germany. pp.128-138, ⟨10.1007/978-3-642-38853-8_12⟩ |
| DOI: | 10.1007/978-3-642-38853-8_12 |
| Popis: | Part 3: Verification; International audience; Nowadays highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging. In ASIPs, it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and the quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and is robust enough to detect also well-hidden bugs. |
| Databáze: | OpenAIRE |
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