Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration
| Autor: | James Harbin, Leandro Soares Indrusiak, Osmar Marchi dos Santos |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Interconnection
Computer science business.industry Design flow Simulation modeling Computer Graphics and Computer-Aided Design Computer Science Applications Network on a chip Embedded system Arbitration Electrical and Electronic Engineering Latency (engineering) Architecture Networks on chip business |
| Zdroj: | ACM Transactions on Design Automation of Electronic Systems. 20:1-22 |
| ISSN: | 1557-7309 1084-4309 |
| DOI: | 10.1145/2755559 |
| Popis: | An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this article, we identify a time-predictable network-on-chip architecture and show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such a feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1,000 times faster when compared to a cycle-accurate model of the same interconnect. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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