Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA
| Autor: | Mariusz Węgrzyn, Agnieszka Dąbrowska-Boruch, Ernest Jamro, Kazimierz Wiatr |
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| Jazyk: | angličtina |
| Rok vydání: | 2021 |
| Předmět: |
Multi-core processor
TK7800-8360 Computer Networks and Communications Computer science Parallel computing Hardware_PERFORMANCEANDRELIABILITY Fault (power engineering) Fault detection and isolation test optimization Hardware and Architecture Control and Systems Engineering Test vector Signal Processing Lookup table Fault coverage Electronics Electrical and Electronic Engineering Fault model Field-programmable gate array FPGA processor testing |
| Zdroj: | Electronics Volume 10 Issue 20 Electronics, Vol 10, Iss 2505, p 2505 (2021) |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics10202505 |
| Popis: | Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable in such a case, only three test vectors are required. Further, local and global test vector selection is also described. |
| Databáze: | OpenAIRE |
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