A novel register renaming technique for out-of-order processors
| Autor: | Hamid Tabani, Jordi Tubella, Antonio González, Jose-Maria Arnau |
|---|---|
| Přispěvatelé: | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors, Universitat Politècnica de Catalunya. CERCLE - Cercle d'Arquitectura |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
Scheme (programming language)
In-flight instructions Speedup Computer science Register renaming supercomputers Register file 02 engineering and technology Physical registers 01 natural sciences Instruction set Precise exceptions 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Register renaming Computer architecture Arithmetic Informàtica::Arquitectura de computadors::Arquitectures paral·leles [Àrees temàtiques de la UPC] Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer.programming_language 010302 applied physics Out-of-order execution Superscalar processor 020202 computer hardware & architecture Producer consumers Register (music) Out-of-order processors High performance computing Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING computer Càlcul intensiu (Informàtica) SPECint Register files |
| Zdroj: | HPCA UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) Recercat. Dipósit de la Recerca de Catalunya instname |
| Popis: | Modern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for every instruction whose destination is a logical register in order to remove false dependences. Physical registers are released in a conservative manner when the same logical register is redefined. For this reason, many cycles may happen between the last read and the release of a physical register, leading to suboptimal utilization of the register file. We have observed that for more than 50% of the instructions in SPECfp and more than 30% of the instructions in SPECint that have a destination register, the produced value has only a single consumer. In this case, the RAW dependence guarantees that the producer-consumer instructions pair will be executed in program order and, hence, the same physical register can be used to store the value produced by both instructions. In this paper, we propose a renaming technique that exploits this property to reduce the pressure on the register file. Our technique leverages physical register sharing by introducing minor changes in the register map table and the issue queue. We also describe how our renaming scheme supports precise exceptions. We evaluated our renaming technique on top of a modern out-of-order processor. Our experimental results show that it provides 6% speedup on average for the SPEC2006 benchmarks. Alternatively, our renaming scheme achieves the same performance while reducing the number of physical registers by 10.5%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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