| Autor: |
Ilia Kempi, Okko Jarvinen, Marko Kosunen, Vishnu Unnikrishnan, Kari Stadius, Jussi Ryynanen |
| Přispěvatelé: |
Department of Electronics and Nanoengineering, Jussi Ryynänen Group, Aalto-yliopisto, Aalto University, Tampere University, Electrical Engineering |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
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| Popis: |
Publisher Copyright: © 2022 IEEE. Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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