A new class of asynchronous A/D converters based on time quantization
| Autor: | Gilles Sicard, Marc Renaudin, E. Allier, Laurent Fesquet |
|---|---|
| Přispěvatelé: | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA) |
| Jazyk: | angličtina |
| Rok vydání: | 2003 |
| Předmět: |
Signal processing
Computer science Quantization (signal processing) 020208 electrical & electronic engineering integrated-smart-devices communicating-objects 020206 networking & telecommunications 02 engineering and technology Integrated circuit design Converters analog-to-digital-converters Effective number of bits Analog signal CMOS Asynchronous communication PACS 85.42 0202 electrical engineering electronic engineering information engineering Electronic engineering power-consumption-reduction [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics |
| Zdroj: | Proceedings-Ninth-International-Symposium-on-Asynchronous-Circuits-and-Systems Proceedings-Ninth-International-Symposium-on-Asynchronous-Circuits-and-Systems, 2003, Vancouver, BC, Canada. pp.196-205, ⟨10.1109/ASYNC.2003.1199179⟩ ASYNC |
| DOI: | 10.1109/ASYNC.2003.1199179⟩ |
| Popis: | This work is a contribution to a drastic change in standard signal processing chains. The main objective is to reduce the power consumption by one or two orders of magnitude. Integrated Smart Devices and Communicating Objects are application domains targeted by this work. In this context, we present a new class of Analog-to-Digital Converters (ADCs), based on an irregular sampling of the analog signal, and an asynchronous design. Because they are not conventional, a complete design methodology is presented. It determines their characteristics given the required effective number of bits and the analog signal properties. it is shown that our approach leads to a significant reduction in terms of hardware complexity and power consumption. A prototype has been designed for speech applications, using the STMicroelectronics 0.18-/spl mu/m CMOS technology. Electrical simulations prove that the factor of merit is increased by more than one order of magnitude compared to synchronous Nyquist ADCs. |
| Databáze: | OpenAIRE |
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