First SOI Tunnel FETs with low-temperature process
| Autor: | C. Diaz Llorente, Sebastien Martinie, Gerard Ghibaudo, M. Vinet, Perrine Batude, C. Le Royer, C. Fenouillet-Beranger, Sorin Cristoloveanu, F. Allain, C-M. V. Lu |
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| Přispěvatelé: | Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Fabrication
Materials science Silicon Tunnel FET Silicon on insulator chemistry.chemical_element low temperature Epitaxy 01 natural sciences tunneling TFET 3D sequential integration 0103 physical sciences [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics BTBT Quantum tunnelling 010302 applied physics business.industry Electrical engineering CoolCube SPER Threshold voltage chemistry Logic gate Optoelectronics business Voltage |
| Zdroj: | 2017 EUROSOI-ULIS Proceedings 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.9-12, ⟨10.1109/ULIS.2017.7962579⟩ |
| DOI: | 10.1109/ULIS.2017.7962579⟩ |
| Popis: | session 1: Nanoscale FETs; International audience; We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage (VTH) of p-mode operating TFETs shows a 300 mV reduction with similar ON state currents (wrt HT reference), opening path towards optimized devices (very low VTH & supply voltage VDD). |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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