Accelerating LTV based homomorphic encryption in reconfigurable hardware
Autor: | Berk Sunar, Erkay Savas, Erdinc Ozturk, Yarkin Doröz |
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Přispěvatelé: | Güneysu, Tim, Handschuh, Helena, Bölüm Yok |
Jazyk: | angličtina |
Rok vydání: | 2015 |
Předmět: |
Virtex
QA075 Electronic computers. Computer science Computer science Homomorphic encryption Parallel computing Reconfigurable computing NTT multiplication Computer engineering Somewhat homomorphic encryption Multiplier (economics) TK7885-7895 Computer engineering. Computer hardware Field-programmable gate array FPGA PCI Express Block cipher Block (data storage) |
Zdroj: | Lecture Notes in Computer Science ISBN: 9783662483237 CHES |
DOI: | 10.1007/978-3-662-48324-4_10 |
Popis: | International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2015 -- 13 September 2015 through 16 September 2015 -- -- 140709 After being introduced in 2009, the first fully homomorphic encryption (FHE) scheme has created significant excitement in academia and industry. Despite rapid advances in the last 6 years, FHE schemes are still not ready for deployment due to an efficiency bottleneck. Here we introduce a custom hardware accelerator optimized for a class of reconfigurable logic to bring LTV based somewhat homomorphic encryption (SWHE) schemes one step closer to deployment in real-life applications. The accelerator we present is connected via a fast PCIe interface to a CPU platform to provide homomorphic evaluation services to any application that needs to support blinded computations. Specifically we introduce a number theoretical transform based multiplier architecture capable of efficiently handling very large polynomials. When synthesized for the Xilinx Virtex 7 family the presented architecture can compute the product of large polynomials in under 6. 25 msec making it the fastest multiplier design of its kind currently available in the literature and is more than 102 times faster than a software implementation. Using this multiplier we can compute a relinearization operation in 526 msec. When used as an accelerator, for instance, to evaluate the AES block cipher, we estimate a per block homomorphic evaluation performance of 442 msec yielding performance gains of 28. 5 and 17 times over similar CPU and GPU implementations, respectively. © International Association for Cryptologic Research 2015. National Science Foundation, NSF: 1319130 -- -- -- Cryptography Research;Etal;Pole D’Excellence Cyber;Serma Technologies;Texas Instruments;Thales, la Region Bretagne |
Databáze: | OpenAIRE |
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