Compensated layout for automated accurate common-centroid capacitor arrays
| Autor: | Andreia Cathelin, Mohamed Dessouky, Marie-Minerve Louerat, Vincent Bourguet, Diaa Khalil, Hani Ragai |
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| Přispěvatelé: | Circuits Intégrés Numériques et Analogiques (CIAN), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS) |
| Předmět: |
Scheme (programming language)
Engineering Analogue electronics Matching (graph theory) business.industry 020208 electrical & electronic engineering Centroid 02 engineering and technology Chip Capacitance 020202 computer hardware & architecture law.invention Capacitor law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering [INFO]Computer Science [cs] business computer Automatic testing ComputingMilieux_MISCELLANEOUS computer.programming_language |
| Zdroj: | Scopus-Elsevier ICEEC 2004-International Conference on Electrical Electronic and Computer Engineering ICEEC 2004-International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.481-484, ⟨10.1109/ICEEC.2004.1374505⟩ |
| DOI: | 10.1109/ICEEC.2004.1374505⟩ |
| Popis: | In this paper, a layout scheme for accurate common-centroid rectangular unit-capacitor arrays is presented with detailed explanation of the rules used to improve matching. This layout technique is combined with a common-centroid arbitrary-value capacitor placement algorithm to form an automatic capacitor array generation tool. Finally, design and measurement results of a test chip that intends to evaluate the effectiveness of this automatic array generation tool are presented. Results indicate significant improvements in |
| Databáze: | OpenAIRE |
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