CMOS Scaling with III-V Channels for Improved Performance and Low Power
Autor: | Raj Jammy, Jungwoo Oh, Prashant Majhi, Richard Hill, Jeff Huang, Wei-Yip Loh, Paul Kirsch, Niti Goel, Joel Barnett, Chanro Park, J. Price |
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Rok vydání: | 2011 |
Předmět: | |
Zdroj: | ECS Transactions. 35:335-344 |
ISSN: | 1938-6737 1938-5862 |
Popis: | The superior transport properties of III-V materials makes them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on 200mm Si MOSFET process flow is presented using an industry standard toolset. Statistically significant data shows that III-V devices can be processed on a Si line with controlled contamination, good uniformity and yield. The Lg = 500 nm device has a drive current of 471 µA/µm (Vgs = Vds = 1V) and intrinsic transconductance of 1005 µS/um. |
Databáze: | OpenAIRE |
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