Simulation of serial RRAM cell based on a Verilog-A compact model
| Autor: | Binbin Yang, Daniel Arumi, Salvador Manich, Alvaro Gomez-Pau, Rosa Rodriguez-Montanes, Juan Bautista Roldan, Mireia Bargallo Gonzalez, Francesca Campabadal, Liang Fang |
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| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Enginyeria Electrònica, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
| Rok vydání: | 2021 |
| Předmět: | |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| DOI: | 10.1109/dcis53048.2021.9666174 |
| Popis: | © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Model-based simulation is one of the effective methods of scientific research. The inherent variability of resistive switching mechanisms has been an obstacle for the massive commercial implementation of the resistive random access memory (RRAM) devices. In this work, we simulated the resistive switching behavior based on an existing RRAM Verilog-A model, in which the simulated switching parameters demonstrated a satisfactory fit with the experimental data by introducing variability into the model. Moreover, a potential application of the troublesome variability was explored in the serial configuration of two RRAM devices, a cell which had been demonstrated to generate unpredictable bits with potential applications in hardware security. Realistic simulation of RRAM based circuits is key for the future development of RRAM based applications. |
| Databáze: | OpenAIRE |
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