Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs
Autor: | Xicai Yue, Chris McLeod, Janice Kiely |
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Jazyk: | angličtina |
Rok vydání: | 2018 |
Předmět: |
Computer Networks and Communications
ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Noise (electronics) Industrial and Manufacturing Engineering successive approximation register (SAR) ADC DAC capacitor array parasitic capacitance thermal noise flicker noise law.invention Parasitic capacitance law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Flicker noise Electrical and Electronic Engineering Physics Dynamic range 020208 electrical & electronic engineering Transistor 020206 networking & telecommunications Successive approximation ADC Computer Science Applications Capacitor Node (circuits) Institute of Bio-Sensing Technology Software Information Systems |
ISSN: | 0952-8091 |
Popis: | Copyright © 2018 Inderscience Enterprises Ltd. This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors’ flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs. |
Databáze: | OpenAIRE |
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