Failure Analysis and Test Solutions for Low-Power SRAMs
| Autor: | Serge Pravossoudovitch, A. Todri, Luigi Dilillo, Arnaud Virazel, N. Badereddine, Patrick Girard, L. B. Zordan, Alberto Bosio |
|---|---|
| Přispěvatelé: | Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Intel Mobile Communications (IMC), Intel Mobile Communications-Intel, European Project, Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM) |
| Jazyk: | angličtina |
| Rok vydání: | 2011 |
| Předmět: |
010302 applied physics
Engineering Random access memory Power gating business.industry memory test 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY SRAM 01 natural sciences failure analysis 020202 computer hardware & architecture Power (physics) [SPI.TRON]Engineering Sciences [physics]/Electronics Power consumption Logic gate 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering power switch Static random-access memory low-power design business Memory test Voltage |
| Zdroj: | 20th IEEE Asian Test Symposium ATS: Asian Test Symposium ATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.459-460, ⟨10.1109/ATS.2011.97⟩ Asian Test Symposium |
| DOI: | 10.1109/ATS.2011.97⟩ |
| Popis: | International audience; Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors. |
| Databáze: | OpenAIRE |
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