A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS
| Autor: | Igor V. Zotov, Mohammed Abdo, Jamil Al Azzeh |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
General Computer Science
lcsh:T58.5-58.64 Computer science business.industry lcsh:Information technology Input-queued switch Pipelining Flit Throughput lcsh:QA75.5-76.95 FIFO-buffer Packet switch Packet switching Multiprocessor lcsh:Electronic computers. Computer science Architecture business Mesh topology Computer network |
| Zdroj: | Jordanian Journal of Computers and Information Technology, Vol 05, Iss 2, Pp 146-162 (2019) |
| ISSN: | 2415-1076 2413-9351 |
| Popis: | In this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a set of independently routed w-bit-wide flits. The device achieves at least 78% throughput for uniformly distributed traffic and an asymptot-ic higher bound of 100%. In contrast to the state-of-the-art VOQ-based switch architectures, the proposed switch is shown to reach its maximum throughput with no internal speedup required and has an order of mag-nitude lower hardware complexity. Compared to existing buffered crossbar non-VOQ switches with typical flit scheduling mechanisms, the proposed device demonstrates slightly higher throughput and substantially short-er delays in some practically important cases. |
| Databáze: | OpenAIRE |
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