CMOS Image Sensor Design and Image Processing Algorithm Implementation for Total Hip Arthroplasty Surgery
| Autor: | Zhihua Wang, Syed Mudassir Hussain, Fasih Ud Din Farrukh, Hong Chen, Shaojie Su |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
medicine.medical_specialty
Computer science Arthroplasty Replacement Hip Population ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION Biomedical Engineering Binary number Image processing 02 engineering and technology Pattern Recognition Automated Image Processing Computer-Assisted 0202 electrical engineering electronic engineering information engineering medicine Humans Electrical and Electronic Engineering Image sensor Field-programmable gate array education Pose education.field_of_study Pixel 020208 electrical & electronic engineering Process (computing) Equipment Design Surgery Semiconductors Algorithm Algorithms |
| Zdroj: | IEEE Transactions on Biomedical Circuits and Systems. 13:1383-1392 |
| ISSN: | 1940-9990 1932-4545 |
| Popis: | As the average age of the population goes higher, the people undergo hip arthroplasty surgery to replace their stiff and painful damaged hip joints. To reduce the risk factor after the surgery we developed a visual aided system in previous works. In order to solve the integration problems of commercial camera with other sensors into the femoral head and to minimize the area and power consumption, in this paper we propose a CMOS image sensor of resolution 200 × 200 specially designed for the application in which each individual pixel measures around 15 μm × 15 μm in size and the image sensor chip size measures about 3.5 mm × 3.5 mm. The proposed sensor is simulated with the input current variations from 2 pA to 100 pA for the individual pixels and the corresponding measurements for each pixel range from 2 mV to 855 mV. Besides, we put forward a new method of pattern detection and recognition in the blood-covered situation, which provides an accurate segmentation of patterns from the blood. All the detected patterns are recognized by generating its right 9-bit binary ID required for the pose estimation calculation. Furthermore, to reduce system power consumption, we implement algorithms on FPGA to process the image data pixel by pixel and transmit it directly to the computer for post-processing. Experimental results show that the pattern detection rate goes as high as 99%, which is 5% better in accuracy compared to the top hat algorithm. The power consumption of the system is 213 mW, which is a 70% decrease compared to our previous work. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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