Defect-location identification for cell-aware test
| Autor: | Jos Huisken, Erik Jan Marinissen, Zhan Gao, Santosh Malagi, Joe Swenton, Kees Goossens |
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| Přispěvatelé: | Electronic Systems, CompSOC Lab- Predictable & Composable Embedded Systems |
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: | |
| Zdroj: | LATS 2019-20th IEEE Latin American Test Symposium LATS BASE-Bielefeld Academic Search Engine |
| Popis: | Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly reduces the amount of test escapes compared to conventional automatic test pattern generation (ATPG). Our CAT flow consists of three steps: (1) defect-location identification (DLI), (2) defect characterization based ondetailed analog simulation of the cells, and (3) cell-aware automatic test pattern generation (ATPG). This paper focuses on Step 1, as quality and cost are determined by the set of cell-internal defect locations considered in the remainder of the flow. Based on technology inputs from the user and a parasitic extraction (PEX) run that analyzes the cell layouts, we derive a set of open defects on and short defects between both transistor terminals and intra-cell interconnects. The full set of defect locations is stored for later use during failure analysis. Through dedicated DLI algorithms, we identify a compact subset of defect locations for defect characterization and ATPG, in which we include onlyone representative defect location for each set of equivalent defects locations. For Cadence’s GPDK045 library, the compact subset contains only 2.8% of the full set of defect locations and reduces the time required for defect characterization with the same ratio. |
| Databáze: | OpenAIRE |
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